1. Field of the Invention
The present invention relates to a pseudo static RAM (random access memory), (RAM), and more specifically, it relates to an improvement in a pseudo static RAM including a dynamic memory cell array and peripheral circuits whose internal operation is controlled in response to change in address signal.
2. Description of the Prior Art
Conventional semiconductor RAMs are roughly classified into a static RAMs and a dynamic RAMs.
In basic structure, the static RAM employs flip-flop circuits as memory cells. The flip-flop circuits employed in the static RAM are in static circuit structure, and hence no stored data will be lost so long as power is applied to the same. Due to such stability in storage, the static RAM is mainly designed in view of facility. In further detail, the static RAM generally requires no external clock. Namely, a desired address can be accessed by simply applying combination of a plurality of signal levels of address signals.
On the other hand, the dynamic RAM employs capacitors as memory cells in basic structure. Namely, the dynamic RAM requires complicated peripheral circuits such as refresh circuits, in order to store information of "0" and "1" depending on whether or not the capacitors store charges. Thus, complicated internal operation of the peripheral circuits is required to access the memory cells of the dynamic RAM, and external clocks are generally required in order to control the internal operation. As compared with the memory cells of the static RAM formed by flip-flops, the memory cells of the dynamic RAM are formed by capacitors of simpler structure and smaller size. Thus, the dynamic RAM can be fabricated in a smaller chip area at a lower cost than the static RAM, to attain the same storage capacity.
As hereinabove described, the static RAM and the dynamic RAM are opposite to each other in that the static RAM is easy to control but high-priced while the dynamic RAM is low-priced but difficult to control.
In recent years, advantages of the static RAM and the dynamic RAM are simultaneously implemented by a semiconductor RAM which is virtually formed by a static RAM but internally structured by a dynamic RAM. Such a semiconductor RAM has pin arrangement and a signal system which are identical to those of the static RAM and employs no external clock similarly to the static RAM, while memory cells thereof are formed by capacitors similarly to the dynamic RAM, to internally utilize clocks. Such an intermediate type RAM is generally called a pseudo static RAM, and disclosed in "A 1 Mb Virtually SRAM" by Sakurai et al., IEEE International Solid-State Circuits Conference, Feb. 21, 1986, pp. 252-253, for example. In such a pseudo static RAM, no clock is present in the signal system of the static RAM and the memory cells are selected in accordance with combination of high and low levels of address signals. Namely, subsequent access is started upon change of the combination. In this case, at least one of a plurality of address signals changes from "H" to "L" or vice versa, and such change is detected so that a pulse is generated to be supplied as a clock required for internal operation of the dynamic RAM.
FIG. 1 is a block diagram showing an example of such a conventional pseudo static RAM. Referring to FIG. 1, memory cells 7.sub.1 to 7.sub.n, sense amplifiers 9.sub.1 to 9.sub.n, a row decoder 5 and a column decoder 10 correspond to basic structure of a general dynamic RAM.
In further detail, each of the memory cells 7.sub.1 to 7.sub.n is formed by a dynamic memory cell having a single capacitor and a single transistor. A first electrode of each capacitor is grounded and a second electrode is connected to a first conducting terminal of the transistor. Second conducting terminals of the transistors of the memory cells 7.sub.1 to 7.sub.n are connected to bit lines BL.sub.1 to BL.sub.n respectively, while control terminals of the transistors are connected to a word line WL. The word lines WL are connected to the row decoder 5, and a dummy word line DWL is connected to a dummy decoder 6. Numerals 8.sub.1 to 8.sub.n indicate parasitic capacitances of the bit lines BL.sub.1 to BL.sub.n respectively. Each of the bit lines BL.sub.1 to BL.sub.n is connected to a power source V.sub.CC through a precharge transistor which is on-off controlled by a signal .phi..sub.P as hereinafter described. The bit lines BL.sub.1 to BL.sub.n are also connected to sense amplifiers 9.sub.1 to 9.sub.n. The column decoder 10 selects one of signals amplified by the sense amplifiers 9.sub.1 to 9.sub.n, to output the same through an output circuit 12 and an output terminal 13.
The pseudo static RAM as shown in FIG. 1 is different from a general dynamic RAM in the following points: Address change detecting circuits 2.sub.1 to 2.sub.n are connected to address signal input terminals 1.sub.1 to 1.sub.n respectively. The address change detecting circuits 2.sub.1 to 2.sub.n directly supply address signal levels applied through the input terminals 1.sub.1 to 1.sub.n to the row decoder 5, while detecting change in address signal level from "H" to "L" or from "L" to "H" to inform a pulse generator 3 of such change. The pulse generator 3 responsively generates a pulse .phi..sub.D as hereinafter described, to supply the same to a timing generator 4. On the basis of the pulse .phi..sub.D, the timing generator 4 generates various timing signals as hereinafter described.
FIG. 2 is a waveform diagram for illustrating the operation of the conventional pseudo static RAM as shown in FIG. 1.
Referring to FIGS. 1 and 2, row address signals are first supplied to the address change detecting circuits 2.sub.1 to 2.sub.n through the input terminals 1.sub.1 to 1.sub.n. When one of the row address signals thus applied changes as shown at FIG. 2(a), corresponding one of the address change detecting circuits 2.sub.1 to 2.sub.n detects the change to inform the pulse generator 3 of the same by a signal. Upon detection of such level change of one of the plurality of row address signals, the pulse generator 3 generates a pulse .phi..sub.D as shown at FIG. 2(b), to supply the same to the timing generator 4. While a general dynamic RAM supplies a clock corresponding to the pulse .phi..sub.D from the exterior, the pseudo static RAM as shown in FIG. 1 is extremely different from such a general dynamic RAM in that the pulse .phi..sub.D corresponding to the clock is generated within the chip on the basis of the address signal change.
On the basis of the pulse .phi..sub.D, the timing generator 4 outputs various timing signals for internal operation of the dynamic RAM.
First, a signal .phi..sub.P at FIG. 2(e) falls from "H" to "L" in response to the pulse .phi..sub.D, whereby the precharge transistors for the bit lines BL.sub.1 to BL.sub.n are turned off. Thus, the bit lines BL.sub.1 to BL.sub.n are cut off from the power sources V.sub.CC in precharged states, to be in preparation for receiving data from the memory cells 7.sub.1 to 7.sub.n Then a signal .phi..sub.WL as shown at FIG. 2(c) rises from "L" to "H", and the row decoder 5 responsively converts levels of the word lines WL from "L" to "H". Thus, the respective transistors of the memory cells 7.sub.1 to 7.sub.n conduct so that the capacitors of the memory cells 7.sub.1 to 7.sub.n are connected to the bit lines BL.sub.1 to BL.sub.n respectively. Namely, when storage contents of the memory cells 7.sub.1 to 7.sub.n are "H" as shown at FIG. 2(f), voltage levels of the bit lines BL.sub.1 to BL.sub.n directly go high as shown at FIG. 2(g), while the voltage levels are slightly lower than the "H" levels as shown at FIG. 2(g) when the storage contents are "L" as shown at FIG. 2(f). Such voltage drop, the value of which is about 200 mV in general, is determined by the ratio of the parasitic capacitances 8.sub.1 to 8.sub.n of the bit lines BL.sub.1 to BL.sub.n to capacitances of the memory cells 7.sub.1 to 7.sub.n. At this time, the voltage levels of the memory cells 7.sub.1 to 7.sub.n are identical to those of the bit lines BL.sub.1 to BL.sub.n, as shown at FIGS. 2(f) and (g).
Then, a signal .phi..sub.SA as shown at FIG. 2(d) rises from "L" to "H", whereby the sense amplifiers 9.sub.1 to 9.sub.n operate to amplify the aforementioned potential difference of 200 mV, thereby to retain the "H" levels of the bit line potentials and correct the incomplete "L" level, being lower by 200 mV than the "H" level, to a complete "L" level, as shown at FIG. 2(g).
It is to be noted here that the voltage levels of the data "L" in the memory cells 7.sub.1 to 7.sub.n are extremely high as shown at FIG. 2(f) within the period in which the word lines WL go high in response to the signal .phi..sub.WL so that the data of the memory cells 7.sub.1 to 7.sub.n are read on the bit lines BL.sub.1 to BL.sub.n, to be amplified by the sense amplifiers 9.sub.1 to 9.sub.n in response to the signal .phi..sub.SA. Namely, the data of the memory cells 7.sub.1 to 7.sub.n are temporarily destroyed, i.e., the same are in the so-called destructive read state in this period.
Then, the column decoder 10 selects one of the signals amplified by the sense amplifiers 9.sub.1 to 9.sub.n to supply the same to the output circuit 12, in response to column address signals supplied to input terminals 11.sub.1 to 11.sub.n. The output circuit 12 outputs the signal of FIG. 2(h) through the output terminal 13.
In the aforementioned conventional pseudo static RAM, consideration must be given to constraints specific to the static RAM. As hereinabove described, the data of the memory cells are temporarily destroyed within a period during operation of the dynamic RAM. Therefore, if the operation is aborted in such a destructive period, the data of the memory cells remained destroyed. Thus, operation, once started, must never be aborted until amplification by the sense amplifiers is completed. Consequently, the width of external clocks is strictly defined in a general dynamic RAM, and such defined width must be absolutely kept in employment of the RAM.
However, the static RAM has rather loose constraints relating to address signals such that, when internal clocks for the dynamic RAM are produced on the basis of address signal change as hereinabove described, the clocks do not satisfy the aforementioned strictly defined width required for the dynamic RAM, and therefore the data of the memory cells may be destroyed.
FIG. 3 is a waveform diagram showing examples of loosely constrained address signals specific to the static RAM. Referring to FIG. 3(a), there is a lag between two sorts of address signals A.sub.1 and A.sub.2. Namely, if an internal clock for starting new operation is generated by change in the address signal A.sub.2 when preceding internal operation is being executed by an internal clock generated by change in the address signal A.sub.1, the preceding internal operation is aborted. FIG. 3(b) shows an address signal which changes in short cycles. Also in this case, preceding internal operation performed by first signal change is aborted halfway by an internal clock generated by second signal change. In the case of FIG. 3(c), an address signal includes noise N. The address change detecting circuits 2.sub.1 to 2.sub.n as shown in FIG. 1 detect such noise N as signal change, leading to a similar result. Such examples (a) to (c) may always take place in actual employment of the static RAM, and hence a pseudo static RAM must be structured so that no malfunction is caused by such address signal change. In view of such a problem, the pseudo static RAM in the aforementioned literature inhibits internal operation in a period of 15 ns from detection of address signal change to prevent a malfunction caused by a small address skew, whereas a malfunction caused by a large skew or noise cannot be prevented by such a method.